
2000 Microchip Technology Inc.
Preliminary
DS41124C-page 139
PIC16C745/765
FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C765)
TABLE 16-7:
PARALLEL SLAVE PORT REQUIREMENTS
RE2/CS
RE0/RD
RE1/WR
RD<7:0>
62
63
64
65
Param No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
62*
TDTV2WRH
Data in valid before WR
↑ or CS↑ (setup time)
20
——
ns
63*
TWRH2DTIWR
↑ or CS↑ to data–in invalid (hold time)
20
——
ns
64
TRDL2DTVRD
↓ and CS↓ to data–out valid
——
80
ns
65*
TRDH2DTIRD
↑ or CS↑ to data–out invalid
10
—
30
ns
*These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: PIC16C765 only.
745cov.book Page 139 Wednesday, August 2, 2000 8:24 AM